dejo @ dejo @kbin.social

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Joined

2 yr. ago

@T4V0 Тhank you.

@T4V0 I use Notepad to write scripts.I don't think it works that way with the code written like this

library ieee;
use ieee.stdlogic1164.all;
use ieee.numericstd.all;
entity tbKitchenTimer is
end tbKitchenTimer;
architecture tb of tbKitchenTimer is
signal clk : stdlogic := '0';
signal reset : stdlogic := '0';
signal start : stdlogic := '0';
signal stop : stdlogic := '0';
signal adjustintervalup : stdlogic := '0';
signal adjustintervaldown : stdlogic := '0';
signal alarm : stdlogic;
constant TbPeriod : time := 10 ns;
signal TbClock : stdlogic := '0';
signal TbSimEnded : stdlogic := '0';
begin
dut : entity work.KitchenTimer
port map
(
clk = clk,
reset = reset,
start = start,
stop = stop,
adjustintervalup = adjustintervalup,
adjustintervaldown = adjustintervaldown,
alarm = alarm
)
TbClock lt;= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0'; -- Clock generation
clk lt;= TbClock;
stimuli : process
variable numticks : natural;
begin
- Reset generation
reset lt;= '1';
wait for 20 ns;
reset lt;= '0';
wait for 20 ns;
- Start the timer
start lt;= '1';
wait for 20 ns;
start lt;= '0';
stop lt;= '1';
- Adjust interval up and down
adjustintervalup lt;= '1';
wait for 10 ns;
start lt;= '1';
stop lt;= '0';
adjustintervalup lt;= '0';
wait for 30 ns;
start lt;= '0';
stop lt;= '1';
adjustintervaldown lt;= '1';
wait for 10 ns;
start lt;= '1';
stop lt;= '0';
adjustintervaldown lt;= '0';
wait for 20 ns;
start lt;= '0';
stop lt;= '1';
adjustintervalup lt;= '1';
wait for 600 ns;
start lt;= '1';
stop lt;= '0';
adjustintervalup lt;= '0';
- Wait for the timer to reach the alarm interval (60 clocks)
wait for 600 ns; -- Simulate for the required time
- Stop the timer
start lt;= '0';
stop lt;= '1';
wait for 100 ns;
- Stop the clock and terminate the simulation
TbSimEnded lt;= '1';
wait;
end process;
end tb;

@T4V0 Thank you so much.

Shouldn't the alarm signal last longer when the alarm interval is increased?

@T4V0

@T4V0 How to How can I include the count signal in the simulation so that it is displayed to me

And this is error:

This is internal schematic of timer555 :

@T4V0 Do you understand Proteus?
I have an error in my schematic, and I can't figure out what it is
Design the internal block diagram of the Timer 555 circuit. Using the designed circuit
make a pulse width modulated (PWM) amplifier. The amplifier works by
at the output it generates a pulse-width modulated signal of a frequency much higher than
frequency of the signal being amplified and often the frequency of the generated signal is 60
kilohertz if it is an audio amplifier. Depending on the intensity of the input signal,
the mean value of the generated signal at the output changes. By using
of the low-pass filter, a signal is obtained which is an amplified version of the input.
The functionality of the amplifier can be demonstrated by applying a sinusoidal signal at the input

And this is whole diagram of project:

@T4V0 Thanks a lot for your help, I appreciate it.

@T4V0
Is the 1/60 Hz set somewhere or is it set in the code itself?
When you say that I must have an "alarming" signal on the simulation, is it actually this "alarm" signal that is presented on the simulation or?
And, do I need to have count signal in simulation?

@T4V0 I just now see your messages, thank you..
In the meantime, I made something like this...
What do you think about the specifications that the project requires, should I stick to your code or should I add something from my own code?
Does your simulation correspond to a time of 1 hour and should there be alarming on the simulation?

Vhdl code:

library ieee;
use ieee.stdlogic1164.all;
use ieee.numericstd.all;
entity KitchenTimer is
port (
clk : in stdlogic; -- Clock input
reset : in stdlogic; -- Reset input
start : in stdlogic; -- Start button input
stop : in stdlogic; -- Stop button input
adjustintervalup : in stdlogic; -- Button for increasing alarm interval
adjustintervaldown : in stdlogic; -- Button for decreasing alarm interval
alarm : out stdlogic -- Alarm output
);
end entity KitchenTimer;
architecture Behavioral of KitchenTimer is
signal count : integer range 0 to 3600000 := 0; -- Adjust range for 1 hour
signal alarming : stdlogic := '0';
signal alarminterval : integer range 600 to 3600000 := 600; -- Adjust range for 1 hour
begin
process (clk, reset)
begin
if reset = '1' then
count lt;= 0;
alarminterval lt;= 600;
elsif risingedge(clk) then
if start = '1' then
count lt;= count + 1;
end if;
if stop = '1' or count = alarminterval then
count lt;= 0;
end if;
if adjustintervalup = '1' then
if alarminterval lt; 3600000 then
alarminterval lt;= alarminterval + 600; -- Adjust increment for 1 minute
end if;
count lt;= 0; -- Reset count when adjusting interval
elsif adjustintervaldown = '1' then
if alarminterval 600 then
alarminterval lt;= alarminterval - 600; -- Adjust decrement for 1 minute
end if;
count lt;= 0; -- Reset count when adjusting interval
end if;
end if;
end process;
alarming lt;= '1' when count = alarminterval else '0';
alarm lt;= alarming;
end architecture Behavioral;

Testbench:

library ieee;
use ieee.stdlogic1164.all;
entity tbKitchenTimer is
end tbKitchenTimer;
architecture tb of tbKitchenTimer is
component KitchenTimer
port (
clk : in stdlogic;
reset : in stdlogic;
start : in stdlogic;
stop : in stdlogic;
adjustintervalup : in stdlogic;
adjustintervaldown : in stdlogic;
alarm : out stdlogic
);
end component;
signal clk : stdlogic := '0';
signal reset : stdlogic := '0';
signal start : stdlogic := '0';
signal stop : stdlogic := '0';
signal adjustintervalup : stdlogic := '0';
signal adjustintervaldown : stdlogic := '0';
signal alarm : stdlogic;
constant TbPeriod : time := 20 ns;
signal TbClock : stdlogic := '0';
signal TbSimEnded : stdlogic := '0';
begin
dut : KitchenTimer
port map (
clk = clk,
reset = reset,
start = start,
stop = stop,
adjustintervalup = adjustintervalup,
adjustintervaldown = adjustintervaldown,
alarm = alarm
);
- Clock generation
TbClock lt;= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
clk lt;= TbClock;
stimuli : process
variable numticks : natural;
begin
- Reset generation
reset lt;= '1';
wait for 200 us;
reset lt;= '0';
wait for 200 us;
- Start the timer
start lt;= '1';
wait for 500 us;
- Adjust interval up and down
adjustintervalup lt;= '1';
wait for 100 us;
adjustintervalup lt;= '0';
wait for 100 us;
adjustintervaldown lt;= '1';
wait for 100 us;
adjustintervaldown lt;= '0';
wait for 100 us;
- Wait for the timer to reach the alarm interval (3600000 clocks)
wait for 72 ms; -- Simulate for the required time
- Stop the timer
start lt;= '0';
wait for 300 us;
- Stop the clock and terminate the simulation
TbSimEnded lt;= '1';
wait;
end process;
end tb;

@T4V0 I
In the meantime, I worked on improving the code.

VHDL code:
llibrary ieee;
use ieee.stdlogic1164.all;
use ieee.numericstd.all;

entity KitchenTimer is
port (
clk : in stdlogic; -- Clock input
reset : in stdlogic; -- Reset input
start : in stdlogic; -- Start button input
stop : in stdlogic; -- Stop button input
adjustintervalup : in stdlogic; -- Button for increasing alarm interval
adjustintervaldown : in stdlogic; -- Button for decreasing alarm interval
alarm : out stdlogic -- Alarm output
);
end entity KitchenTimer;
architecture Behavioral of KitchenTimer is
signal count : integer range 0 to 3600000 := 0; -- Adjust range for 1 hour
signal alarming : stdlogic := '0';
signal alarminterval : integer range 600 to 3600000 := 600; -- Adjust range for 1 hour
begin
process (clk, reset)
begin
if reset = '1' then
count lt;= 0;
alarminterval lt;= 600;
elsif risingedge(clk) then
if start = '1' then
count lt;= count + 1;
end if;
if stop = '1' or count = alarminterval then
count lt;= 0;
end if;
if adjustintervalup = '1' then
if alarminterval lt; 3600000 then
alarminterval lt;= alarminterval + 600; -- Adjust increment for 1 minute
end if;
count lt;= 0; -- Reset count when adjusting interval
elsif adjustintervaldown = '1' then
if alarminterval 600 then
alarminterval lt;= alarminterval - 600; -- Adjust decrement for 1 minute
end if;
count lt;= 0; -- Reset count when adjusting interval
end if;
end if;
end process;
alarming lt;= '1' when count = alarminterval else '0';
alarm lt;= alarming;
end architecture Behavioral;

Testbench:

library ieee;
use ieee.stdlogic1164.all;

entity tbKitchenTimer is
end tbKitchenTimer;
architecture tb of tbKitchenTimer is
component KitchenTimer
port (
clk : in stdlogic;
reset : in stdlogic;
start : in stdlogic;
stop : in stdlogic;
adjustintervalup : in stdlogic;
adjustintervaldown : in stdlogic;
alarm : out stdlogic
);
end component;
signal clk : stdlogic := '0';
signal reset : stdlogic := '0';
signal start : stdlogic := '0';
signal stop : stdlogic := '0';
signal adjustintervalup : stdlogic := '0';
signal adjustintervaldown : stdlogic := '0';
signal alarm : stdlogic;
constant TbPeriod : time := 20 ns;
signal TbClock : stdlogic := '0';
signal TbSimEnded : stdlogic := '0';
begin
dut : KitchenTimer
port map (
clk = clk,
reset = reset,
start = start,
stop = stop,
adjustintervalup = adjustintervalup,
adjustintervaldown = adjustintervaldown,
alarm = alarm
);
- Clock generation
TbClock lt;= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
clk lt;= TbClock;
stimuli : process
variable numticks : natural;
begin
- Reset generation
reset lt;= '1';
wait for 200 us;
reset lt;= '0';
wait for 200 us;
- Start the timer
start lt;= '1';
wait for 500 us;
- Adjust interval up and down
adjustintervalup lt;= '1';
wait for 100 us;
adjustintervalup lt;= '0';
wait for 100 us;
adjustintervaldown lt;= '1';
wait for 100 us;
adjustintervaldown lt;= '0';
wait for 100 us;
- Wait for the timer to reach the alarm interval (3600000 clocks)
wait for 72 ms; -- Simulate for the required time
- Stop the timer
start lt;= '0';
wait for 300 us;
- Stop the clock and terminate the simulation
TbSimEnded lt;= '1';
wait;
end process;
end tb;

And this is simulation:

@T4V0 Hello, I've been doing a lot of research on this project these days and I've brought the code to a better level, I hope... But I'm not sure if this simulation...

This is VHDL code:
library ieee;

use ieee.stdlogic1164.all;

use ieee.numericstd.all;

entity KitchenTimer is

port (

clk : in stdlogic; -- Clock input

reset : in stdlogic; -- Reset input

start : in stdlogic; -- Start button input

stop : in stdlogic; -- Stop button input

adjustintervalup : in stdlogic; -- Button for increasing alarm interval

adjustintervaldown : in stdlogic; -- Button for decreasing alarm interval

alarm : out stdlogic -- Alarm output

);

end entity KitchenTimer;

architecture Behavioral of KitchenTimer is

signal count : integer range 0 to 3600000 := 0; -- Adjust range for 1 hour

signal alarming : stdlogic := '0';

signal alarminterval : integer range 600 to 3600000 := 600; -- Adjust range for 1 hour

begin

process (clk, reset)

begin

if reset = '1' then

count lt;= 0;

alarming lt;= '0';

alarminterval lt;= 600;

elsif risingedge(clk) then

if start = '1' then

count lt;= count + 1;

end if;

if stop = '1' or count = alarminterval then

count lt;= 0;

end if;

if adjustintervalup = '1' then

if alarminterval lt; 3600000 then

alarminterval lt;= alarminterval + 600; -- Adjust increment for 1 minute

end if;

elsif adjustintervaldown = '1' then

if alarminterval 600 then

alarminterval lt;= alarminterval - 600; -- Adjust decrement for 1 minute

end if;

end if;

end if;

end process;

alarming lt;= '1' when count = alarminterval else '0';

alarm lt;= alarming;

end architecture Behavioral;

This is Testbench:
library ieee;

use ieee.stdlogic1164.all;

entity tbKitchenTimer is

end tbKitchenTimer;

architecture tb of tbKitchenTimer is

component KitchenTimer

port (

clk : in stdlogic;

reset : in stdlogic;

start : in stdlogic;

stop : in stdlogic;

adjustintervalup : in stdlogic;

adjustintervaldown : in stdlogic;

alarm : out stdlogic

);

end component;

signal clk : stdlogic := '0';

signal reset : stdlogic := '0';

signal start : stdlogic := '0';

signal stop : stdlogic := '0';

signal adjustintervalup : stdlogic := '0';

signal adjustintervaldown : stdlogic := '0';

signal alarm : stdlogic;

constant TbPeriod : time := 1 us; -- Set the clock period to 1us

signal TbClock : stdlogic := '0';

signal TbSimEnded : stdlogic := '0';

begin

dut : KitchenTimer

port map (

clk = clk,

reset = reset,

start = start,

stop = stop,

adjustintervalup = adjustintervalup,

adjustintervaldown = adjustintervaldown,

alarm = alarm

);

- Clock generation

TbClock lt;= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';

clk lt;= TbClock;

stimuli : process

begin

- Reset generation

reset lt;= '1';

wait for 20 us; -- Adjust delay to fit the new clock period

reset lt;= '0';

- Add your stimuli and test cases here

- For example:

start lt;= '1';

wait for 50 us; -- Adjust delay to fit the new clock period

start lt;= '0';

wait for 400 us; -- Adjust delay to fit the new clock period

adjustintervalup lt;= '1';

wait for 20 us; -- Adjust delay to fit the new clock period

adjustintervalup lt;= '0';

wait for 50 us; -- Adjust delay to fit the new clock period

adjustintervaldown lt;= '1';

wait for 20 us; -- Adjust delay to fit the new clock period

adjustintervaldown lt;= '0';

wait for 50 us; -- Adjust delay to fit the new clock period

- ...

- Stop the clock and hence terminate the simulation

TbSimEnded lt;= '1';

wait;

end process;

end tb;

- Configuration block below is required by some simulators. Usually no need to edit.

configuration cfgtbKitchenTimer of tbKitchenTimer is

for tb

end for;

end cfgtbKitchenTimer;
And this is result of simulation:

@T4V0 Thanks for the answer, but I think I didn't understand you very well, can you send me the code with the modifications so that I know what exactly you mean?
Thank you very much, in advance