{"person_view":{"person":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"counts":{"person_id":1638447,"post_count":1,"comment_count":14},"is_admin":false},"comments":[{"comment":{"id":1979021,"creator_id":1638447,"post_id":821313,"content":"[@T4V0](https://kbin.social/u/T4V0) Тhank you.","removed":false,"published":"2023-09-12T08:59:24Z","deleted":false,"ap_id":"https://kbin.social/m/science/p/1508983/-/reply/3015497","local":false,"path":"0.1497215.1566279.1616298.1624063.1627028.1651483.1690824.1786946.1791583.1792928.1796436.1951080.1954916.1956511.1957534.1979021","distinguished":false,"language_id":0},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"counts":{"comment_id":1979021,"score":1,"upvotes":1,"downvotes":0,"published":"2023-09-12T08:59:24Z","child_count":0},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"subscribed":"NotSubscribed","saved":false,"creator_blocked":false},{"comment":{"id":1956511,"creator_id":1638447,"post_id":821313,"content":"[@T4V0](https://kbin.social/u/T4V0) I use Notepad to write scripts.I don't think it works that way with the code written like this\n\n\\*\\*library ieee; \nuse ieee.std\\_logic\\_1164.all; \nuse ieee.numeric\\_std.all; \nentity tb\\_Kitchen\\_Timer is \nend tb\\_Kitchen\\_Timer; \narchitecture tb of tb\\_Kitchen\\_Timer is \nsignal clk : std\\_logic := '0'; \nsignal reset : std\\_logic := '0'; \nsignal start : std\\_logic := '0'; \nsignal stop : std\\_logic := '0'; \nsignal adjust\\_interval\\_up : std\\_logic := '0'; \nsignal adjust\\_interval\\_down : std\\_logic := '0'; \nsignal alarm : std\\_logic; \nconstant TbPeriod : time := 10 ns; \nsignal TbClock : std\\_logic := '0'; \nsignal TbSimEnded : std\\_logic := '0'; \nbegin \ndut : entity work.Kitchen\\_Timer \nport map \n( \nclk =\\> clk, \nreset =\\> reset, \nstart =\\> start, \nstop =\\> stop, \nadjust\\_interval\\_up =\\> adjust\\_interval\\_up, \nadjust\\_interval\\_down =\\> adjust\\_interval\\_down, \nalarm =\\> alarm \n) \nTbClock \\<= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0'; -- Clock generation \nclk \\<= TbClock; \nstimuli : process \nvariable num\\_ticks : natural; \nbegin \n\\-- Reset generation \nreset \\<= '1'; \nwait for 20 ns; \nreset \\<= '0'; \nwait for 20 ns; \n\\-- Start the timer \nstart \\<= '1'; \nwait for 20 ns; \nstart \\<= '0'; \nstop \\<= '1'; \n\\-- Adjust interval up and down \nadjust\\_interval\\_up \\<= '1'; \nwait for 10 ns; \nstart \\<= '1'; \nstop \\<= '0'; \nadjust\\_interval\\_up \\<= '0'; \nwait for 30 ns; \nstart \\<= '0'; \nstop \\<= '1'; \nadjust\\_interval\\_down \\<= '1'; \nwait for 10 ns; \nstart \\<= '1'; \nstop \\<= '0'; \nadjust\\_interval\\_down \\<= '0'; \nwait for 20 ns; \nstart \\<= '0'; \nstop \\<= '1'; \nadjust\\_interval\\_up \\<= '1'; \nwait for 600 ns; \nstart \\<= '1'; \nstop \\<= '0'; \nadjust\\_interval\\_up \\<= '0'; \n\\-- Wait for the timer to reach the alarm interval (60 clocks) \nwait for 600 ns; -- Simulate for the required time \n\\-- Stop the timer \nstart \\<= '0'; \nstop \\<= '1'; \nwait for 100 ns; \n\\-- Stop the clock and terminate the simulation \nTbSimEnded \\<= '1'; \nwait; \nend process; \nend tb; \n\\*\\*","removed":false,"published":"2023-09-11T14:00:35Z","updated":"2023-09-11T14:01:06Z","deleted":false,"ap_id":"https://kbin.social/m/science/p/1508983/-/reply/2994043","local":false,"path":"0.1497215.1566279.1616298.1624063.1627028.1651483.1690824.1786946.1791583.1792928.1796436.1951080.1954916.1956511","distinguished":false,"language_id":0},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"counts":{"comment_id":1956511,"score":1,"upvotes":1,"downvotes":0,"published":"2023-09-11T14:00:35Z","child_count":2},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"subscribed":"NotSubscribed","saved":false,"creator_blocked":false},{"comment":{"id":1956416,"creator_id":1638447,"post_id":821313,"content":"[@T4V0](https://kbin.social/u/T4V0) Thank you so much.","removed":false,"published":"2023-09-11T13:57:05Z","deleted":false,"ap_id":"https://kbin.social/m/science/p/1508983/-/reply/2993970","local":false,"path":"0.1497215.1566279.1616298.1624063.1627028.1651483.1690824.1786946.1791583.1792928.1796436.1951080.1951209.1955176.1956416","distinguished":false,"language_id":0},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"counts":{"comment_id":1956416,"score":1,"upvotes":1,"downvotes":0,"published":"2023-09-11T13:57:05Z","child_count":0},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"subscribed":"NotSubscribed","saved":false,"creator_blocked":false},{"comment":{"id":1951209,"creator_id":1638447,"post_id":821313,"content":"Shouldn't the alarm signal last longer when the alarm interval is increased?\n\n[@T4V0](https://kbin.social/u/T4V0)","removed":false,"published":"2023-09-11T08:34:22Z","deleted":false,"ap_id":"https://kbin.social/m/science/p/1508983/-/reply/2988596","local":false,"path":"0.1497215.1566279.1616298.1624063.1627028.1651483.1690824.1786946.1791583.1792928.1796436.1951080.1951209","distinguished":false,"language_id":0},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"counts":{"comment_id":1951209,"score":1,"upvotes":1,"downvotes":0,"published":"2023-09-11T08:34:22Z","child_count":2},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"subscribed":"NotSubscribed","saved":false,"creator_blocked":false},{"comment":{"id":1951080,"creator_id":1638447,"post_id":821313,"content":"[@T4V0](https://kbin.social/u/T4V0) How to How can I include the count signal in the simulation so that it is displayed to me","removed":false,"published":"2023-09-11T08:24:24Z","deleted":false,"ap_id":"https://kbin.social/m/science/p/1508983/-/reply/2988433","local":false,"path":"0.1497215.1566279.1616298.1624063.1627028.1651483.1690824.1786946.1791583.1792928.1796436.1951080","distinguished":false,"language_id":0},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"counts":{"comment_id":1951080,"score":1,"upvotes":1,"downvotes":0,"published":"2023-09-11T08:24:24Z","child_count":7},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"subscribed":"NotSubscribed","saved":false,"creator_blocked":false},{"comment":{"id":1815003,"creator_id":1638447,"post_id":821313,"content":"And this is error:","removed":false,"published":"2023-09-06T08:44:47Z","deleted":false,"ap_id":"https://kbin.social/m/science/p/1508983/-/reply/2856821","local":false,"path":"0.1814845.1814904.1815003","distinguished":false,"language_id":0},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"counts":{"comment_id":1815003,"score":1,"upvotes":1,"downvotes":0,"published":"2023-09-06T08:44:47Z","child_count":0},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"subscribed":"NotSubscribed","saved":false,"creator_blocked":false},{"comment":{"id":1814904,"creator_id":1638447,"post_id":821313,"content":"This is internal schematic of timer555 :","removed":false,"published":"2023-09-06T08:37:58Z","deleted":false,"ap_id":"https://kbin.social/m/science/p/1508983/-/reply/2856716","local":false,"path":"0.1814845.1814904","distinguished":false,"language_id":0},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"counts":{"comment_id":1814904,"score":1,"upvotes":1,"downvotes":0,"published":"2023-09-06T08:37:58Z","child_count":1},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"subscribed":"NotSubscribed","saved":false,"creator_blocked":false},{"comment":{"id":1814845,"creator_id":1638447,"post_id":821313,"content":"[@T4V0](https://kbin.social/u/T4V0) Do you understand Proteus? \nI have an error in my schematic, and I can't figure out what it is \n**Design the internal block diagram of the Timer 555 circuit. Using the designed circuit \nmake a pulse width modulated (PWM) amplifier. The amplifier works by \nat the output it generates a pulse-width modulated signal of a frequency much higher than \nfrequency of the signal being amplified and often the frequency of the generated signal is 60 \nkilohertz if it is an audio amplifier. Depending on the intensity of the input signal, \nthe mean value of the generated signal at the output changes. By using \nof the low-pass filter, a signal is obtained which is an amplified version of the input. \nThe functionality of the amplifier can be demonstrated by applying a sinusoidal signal at the input**\n\nAnd this is whole diagram of project:","removed":false,"published":"2023-09-06T08:33:25Z","updated":"2023-09-06T08:43:06Z","deleted":false,"ap_id":"https://kbin.social/m/science/p/1508983/-/reply/2856572","local":false,"path":"0.1814845","distinguished":false,"language_id":0},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"counts":{"comment_id":1814845,"score":1,"upvotes":1,"downvotes":0,"published":"2023-09-06T08:33:25Z","child_count":2},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"subscribed":"NotSubscribed","saved":false,"creator_blocked":false},{"comment":{"id":1814784,"creator_id":1638447,"post_id":821313,"content":"[@T4V0](https://kbin.social/u/T4V0) Thanks a lot for your help, I appreciate it.","removed":false,"published":"2023-09-06T08:28:41Z","deleted":false,"ap_id":"https://kbin.social/m/science/p/1508983/-/reply/2856514","local":false,"path":"0.1497215.1566279.1616298.1624063.1627028.1651483.1690824.1786946.1791583.1792928.1796436.1814784","distinguished":false,"language_id":0},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"counts":{"comment_id":1814784,"score":1,"upvotes":1,"downvotes":0,"published":"2023-09-06T08:28:41Z","child_count":0},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"subscribed":"NotSubscribed","saved":false,"creator_blocked":false},{"comment":{"id":1792928,"creator_id":1638447,"post_id":821313,"content":"[@T4V0](https://kbin.social/u/T4V0) \nIs the 1/60 Hz set somewhere or is it set in the code itself? \nWhen you say that I must have an \"alarming\" signal on the simulation, is it actually this \"alarm\" signal that is presented on the simulation or? \nAnd, do I need to have count signal in simulation?","removed":false,"published":"2023-09-05T13:40:34Z","updated":"2023-09-05T14:52:09Z","deleted":false,"ap_id":"https://kbin.social/m/science/p/1508983/-/reply/2833898","local":false,"path":"0.1497215.1566279.1616298.1624063.1627028.1651483.1690824.1786946.1791583.1792928","distinguished":false,"language_id":0},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"counts":{"comment_id":1792928,"score":1,"upvotes":1,"downvotes":0,"published":"2023-09-05T13:40:34Z","child_count":10},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"subscribed":"NotSubscribed","saved":false,"creator_blocked":false},{"comment":{"id":1786946,"creator_id":1638447,"post_id":821313,"content":"[@T4V0](https://kbin.social/u/T4V0) I just now see your messages, thank you.. \nIn the meantime, I made something like this... \nWhat do you think about the specifications that the project requires, should I stick to your code or should I add something from my own code? \nDoes your simulation correspond to a time of 1 hour and should there be alarming on the simulation?\n\nVhdl code:\n\nlibrary ieee; \nuse ieee.std\\_logic\\_1164.all; \nuse ieee.numeric\\_std.all; \nentity Kitchen\\_Timer is \nport ( \nclk : in std\\_logic; -- Clock input \nreset : in std\\_logic; -- Reset input \nstart : in std\\_logic; -- Start button input \nstop : in std\\_logic; -- Stop button input \nadjust\\_interval\\_up : in std\\_logic; -- Button for increasing alarm interval \nadjust\\_interval\\_down : in std\\_logic; -- Button for decreasing alarm interval \nalarm : out std\\_logic -- Alarm output \n); \nend entity Kitchen\\_Timer; \narchitecture Behavioral of Kitchen\\_Timer is \nsignal count : integer range 0 to 3600000 := 0; -- Adjust range for 1 hour \nsignal alarming : std\\_logic := '0'; \nsignal alarm\\_interval : integer range 600 to 3600000 := 600; -- Adjust range for 1 hour \nbegin \nprocess (clk, reset) \nbegin \nif reset = '1' then \ncount \\<= 0; \nalarm\\_interval \\<= 600; \nelsif rising\\_edge(clk) then \nif start = '1' then \ncount \\<= count + 1; \nend if; \nif stop = '1' or count = alarm\\_interval then \ncount \\<= 0; \nend if; \nif adjust\\_interval\\_up = '1' then \nif alarm\\_interval \\< 3600000 then \nalarm\\_interval \\<= alarm\\_interval + 600; -- Adjust increment for 1 minute \nend if; \ncount \\<= 0; -- Reset count when adjusting interval \nelsif adjust\\_interval\\_down = '1' then \nif alarm\\_interval \\> 600 then \nalarm\\_interval \\<= alarm\\_interval - 600; -- Adjust decrement for 1 minute \nend if; \ncount \\<= 0; -- Reset count when adjusting interval \nend if; \nend if; \nend process; \nalarming \\<= '1' when count \\>= alarm\\_interval else '0'; \nalarm \\<= alarming; \nend architecture Behavioral;\n\nTestbench:\n\nlibrary ieee; \nuse ieee.std\\_logic\\_1164.all; \nentity tb\\_Kitchen\\_Timer is \nend tb\\_Kitchen\\_Timer; \narchitecture tb of tb\\_Kitchen\\_Timer is \ncomponent Kitchen\\_Timer \nport ( \nclk : in std\\_logic; \nreset : in std\\_logic; \nstart : in std\\_logic; \nstop : in std\\_logic; \nadjust\\_interval\\_up : in std\\_logic; \nadjust\\_interval\\_down : in std\\_logic; \nalarm : out std\\_logic \n); \nend component; \nsignal clk : std\\_logic := '0'; \nsignal reset : std\\_logic := '0'; \nsignal start : std\\_logic := '0'; \nsignal stop : std\\_logic := '0'; \nsignal adjust\\_interval\\_up : std\\_logic := '0'; \nsignal adjust\\_interval\\_down : std\\_logic := '0'; \nsignal alarm : std\\_logic; \nconstant TbPeriod : time := 20 ns; \nsignal TbClock : std\\_logic := '0'; \nsignal TbSimEnded : std\\_logic := '0'; \nbegin \ndut : Kitchen\\_Timer \nport map ( \nclk =\\> clk, \nreset =\\> reset, \nstart =\\> start, \nstop =\\> stop, \nadjust\\_interval\\_up =\\> adjust\\_interval\\_up, \nadjust\\_interval\\_down =\\> adjust\\_interval\\_down, \nalarm =\\> alarm \n); \n\\-- Clock generation \nTbClock \\<= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0'; \nclk \\<= TbClock; \nstimuli : process \nvariable num\\_ticks : natural; \nbegin \n\\-- Reset generation \nreset \\<= '1'; \nwait for 200 us; \nreset \\<= '0'; \nwait for 200 us; \n\\-- Start the timer \nstart \\<= '1'; \nwait for 500 us; \n\\-- Adjust interval up and down \nadjust\\_interval\\_up \\<= '1'; \nwait for 100 us; \nadjust\\_interval\\_up \\<= '0'; \nwait for 100 us; \nadjust\\_interval\\_down \\<= '1'; \nwait for 100 us; \nadjust\\_interval\\_down \\<= '0'; \nwait for 100 us; \n\\-- Wait for the timer to reach the alarm interval (3600000 clocks) \nwait for 72 ms; -- Simulate for the required time \n\\-- Stop the timer \nstart \\<= '0'; \nwait for 300 us; \n\\-- Stop the clock and terminate the simulation \nTbSimEnded \\<= '1'; \nwait; \nend process; \nend tb;","removed":false,"published":"2023-09-05T07:31:35Z","updated":"2023-09-05T12:08:20Z","deleted":false,"ap_id":"https://kbin.social/m/science/p/1508983/-/reply/2827262","local":false,"path":"0.1497215.1566279.1616298.1624063.1627028.1651483.1690824.1786946","distinguished":false,"language_id":0},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"counts":{"comment_id":1786946,"score":1,"upvotes":1,"downvotes":0,"published":"2023-09-05T07:31:35Z","child_count":12},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"subscribed":"NotSubscribed","saved":false,"creator_blocked":false},{"comment":{"id":1651483,"creator_id":1638447,"post_id":821313,"content":"[@T4V0](https://kbin.social/u/T4V0) I \nIn the meantime, I worked on improving the code.\n\nVHDL code: \nllibrary ieee; \nuse ieee.std\\_logic\\_1164.all; \nuse ieee.numeric\\_std.all;\n\nentity Kitchen\\_Timer is \nport ( \nclk : in std\\_logic; -- Clock input \nreset : in std\\_logic; -- Reset input \nstart : in std\\_logic; -- Start button input \nstop : in std\\_logic; -- Stop button input \nadjust\\_interval\\_up : in std\\_logic; -- Button for increasing alarm interval \nadjust\\_interval\\_down : in std\\_logic; -- Button for decreasing alarm interval \nalarm : out std\\_logic -- Alarm output \n); \nend entity Kitchen\\_Timer; \narchitecture Behavioral of Kitchen\\_Timer is \nsignal count : integer range 0 to 3600000 := 0; -- Adjust range for 1 hour \nsignal alarming : std\\_logic := '0'; \nsignal alarm\\_interval : integer range 600 to 3600000 := 600; -- Adjust range for 1 hour \nbegin \nprocess (clk, reset) \nbegin \nif reset = '1' then \ncount \\<= 0; \nalarm\\_interval \\<= 600; \nelsif rising\\_edge(clk) then \nif start = '1' then \ncount \\<= count + 1; \nend if; \nif stop = '1' or count = alarm\\_interval then \ncount \\<= 0; \nend if; \nif adjust\\_interval\\_up = '1' then \nif alarm\\_interval \\< 3600000 then \nalarm\\_interval \\<= alarm\\_interval + 600; -- Adjust increment for 1 minute \nend if; \ncount \\<= 0; -- Reset count when adjusting interval \nelsif adjust\\_interval\\_down = '1' then \nif alarm\\_interval \\> 600 then \nalarm\\_interval \\<= alarm\\_interval - 600; -- Adjust decrement for 1 minute \nend if; \ncount \\<= 0; -- Reset count when adjusting interval \nend if; \nend if; \nend process; \nalarming \\<= '1' when count \\>= alarm\\_interval else '0'; \nalarm \\<= alarming; \nend architecture Behavioral;\n\nTestbench:\n\nlibrary ieee; \nuse ieee.std\\_logic\\_1164.all;\n\nentity tb\\_Kitchen\\_Timer is \nend tb\\_Kitchen\\_Timer; \narchitecture tb of tb\\_Kitchen\\_Timer is \ncomponent Kitchen\\_Timer \nport ( \nclk : in std\\_logic; \nreset : in std\\_logic; \nstart : in std\\_logic; \nstop : in std\\_logic; \nadjust\\_interval\\_up : in std\\_logic; \nadjust\\_interval\\_down : in std\\_logic; \nalarm : out std\\_logic \n); \nend component; \nsignal clk : std\\_logic := '0'; \nsignal reset : std\\_logic := '0'; \nsignal start : std\\_logic := '0'; \nsignal stop : std\\_logic := '0'; \nsignal adjust\\_interval\\_up : std\\_logic := '0'; \nsignal adjust\\_interval\\_down : std\\_logic := '0'; \nsignal alarm : std\\_logic; \nconstant TbPeriod : time := 20 ns; \nsignal TbClock : std\\_logic := '0'; \nsignal TbSimEnded : std\\_logic := '0'; \nbegin \ndut : Kitchen\\_Timer \nport map ( \nclk =\\> clk, \nreset =\\> reset, \nstart =\\> start, \nstop =\\> stop, \nadjust\\_interval\\_up =\\> adjust\\_interval\\_up, \nadjust\\_interval\\_down =\\> adjust\\_interval\\_down, \nalarm =\\> alarm \n); \n\\-- Clock generation \nTbClock \\<= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0'; \nclk \\<= TbClock; \nstimuli : process \nvariable num\\_ticks : natural; \nbegin \n\\-- Reset generation \nreset \\<= '1'; \nwait for 200 us; \nreset \\<= '0'; \nwait for 200 us; \n\\-- Start the timer \nstart \\<= '1'; \nwait for 500 us; \n\\-- Adjust interval up and down \nadjust\\_interval\\_up \\<= '1'; \nwait for 100 us; \nadjust\\_interval\\_up \\<= '0'; \nwait for 100 us; \nadjust\\_interval\\_down \\<= '1'; \nwait for 100 us; \nadjust\\_interval\\_down \\<= '0'; \nwait for 100 us; \n\\-- Wait for the timer to reach the alarm interval (3600000 clocks) \nwait for 72 ms; -- Simulate for the required time \n\\-- Stop the timer \nstart \\<= '0'; \nwait for 300 us; \n\\-- Stop the clock and terminate the simulation \nTbSimEnded \\<= '1'; \nwait; \nend process; \nend tb;\n\nAnd this is simulation:","removed":false,"published":"2023-08-31T12:26:26Z","updated":"2023-08-31T20:28:56Z","deleted":false,"ap_id":"https://kbin.social/m/science/p/1508983/-/reply/2704244","local":false,"path":"0.1497215.1566279.1616298.1624063.1627028.1651483","distinguished":false,"language_id":0},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"counts":{"comment_id":1651483,"score":2,"upvotes":2,"downvotes":0,"published":"2023-08-31T12:26:26Z","child_count":14},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"subscribed":"NotSubscribed","saved":false,"creator_blocked":false},{"comment":{"id":1624063,"creator_id":1638447,"post_id":821313,"content":"[@T4V0](https://kbin.social/u/T4V0) Hello, I've been doing a lot of research on this project these days and I've brought the code to a better level, I hope... But I'm not sure if this simulation...\n\nThis is VHDL code: \nlibrary ieee;\n\nuse ieee.std\\_logic\\_1164.all;\n\nuse ieee.numeric\\_std.all;\n\nentity Kitchen\\_Timer is\n\nport (\n\nclk : in std\\_logic; -- Clock input\n\nreset : in std\\_logic; -- Reset input\n\nstart : in std\\_logic; -- Start button input\n\nstop : in std\\_logic; -- Stop button input\n\nadjust\\_interval\\_up : in std\\_logic; -- Button for increasing alarm interval\n\nadjust\\_interval\\_down : in std\\_logic; -- Button for decreasing alarm interval\n\nalarm : out std\\_logic -- Alarm output\n\n);\n\nend entity Kitchen\\_Timer;\n\narchitecture Behavioral of Kitchen\\_Timer is\n\nsignal count : integer range 0 to 3600000 := 0; -- Adjust range for 1 hour\n\nsignal alarming : std\\_logic := '0';\n\nsignal alarm\\_interval : integer range 600 to 3600000 := 600; -- Adjust range for 1 hour\n\nbegin\n\nprocess (clk, reset)\n\nbegin\n\nif reset = '1' then\n\ncount \\<= 0;\n\nalarming \\<= '0';\n\nalarm\\_interval \\<= 600;\n\nelsif rising\\_edge(clk) then\n\nif start = '1' then\n\ncount \\<= count + 1;\n\nend if;\n\nif stop = '1' or count = alarm\\_interval then\n\ncount \\<= 0;\n\nend if;\n\nif adjust\\_interval\\_up = '1' then\n\nif alarm\\_interval \\< 3600000 then\n\nalarm\\_interval \\<= alarm\\_interval + 600; -- Adjust increment for 1 minute\n\nend if;\n\nelsif adjust\\_interval\\_down = '1' then\n\nif alarm\\_interval \\> 600 then\n\nalarm\\_interval \\<= alarm\\_interval - 600; -- Adjust decrement for 1 minute\n\nend if;\n\nend if;\n\nend if;\n\nend process;\n\nalarming \\<= '1' when count \\>= alarm\\_interval else '0';\n\nalarm \\<= alarming;\n\nend architecture Behavioral;\n\nThis is Testbench: \nlibrary ieee;\n\nuse ieee.std\\_logic\\_1164.all;\n\nentity tb\\_Kitchen\\_Timer is\n\nend tb\\_Kitchen\\_Timer;\n\narchitecture tb of tb\\_Kitchen\\_Timer is\n\ncomponent Kitchen\\_Timer\n\nport (\n\nclk : in std\\_logic;\n\nreset : in std\\_logic;\n\nstart : in std\\_logic;\n\nstop : in std\\_logic;\n\nadjust\\_interval\\_up : in std\\_logic;\n\nadjust\\_interval\\_down : in std\\_logic;\n\nalarm : out std\\_logic\n\n);\n\nend component;\n\nsignal clk : std\\_logic := '0';\n\nsignal reset : std\\_logic := '0';\n\nsignal start : std\\_logic := '0';\n\nsignal stop : std\\_logic := '0';\n\nsignal adjust\\_interval\\_up : std\\_logic := '0';\n\nsignal adjust\\_interval\\_down : std\\_logic := '0';\n\nsignal alarm : std\\_logic;\n\nconstant TbPeriod : time := 1 us; -- Set the clock period to 1us\n\nsignal TbClock : std\\_logic := '0';\n\nsignal TbSimEnded : std\\_logic := '0';\n\nbegin\n\ndut : Kitchen\\_Timer\n\nport map (\n\nclk =\\> clk,\n\nreset =\\> reset,\n\nstart =\\> start,\n\nstop =\\> stop,\n\nadjust\\_interval\\_up =\\> adjust\\_interval\\_up,\n\nadjust\\_interval\\_down =\\> adjust\\_interval\\_down,\n\nalarm =\\> alarm\n\n);\n\n\\-- Clock generation\n\nTbClock \\<= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\nclk \\<= TbClock;\n\nstimuli : process\n\nbegin\n\n\\-- Reset generation\n\nreset \\<= '1';\n\nwait for 20 us; -- Adjust delay to fit the new clock period\n\nreset \\<= '0';\n\n\\-- Add your stimuli and test cases here\n\n\\-- For example:\n\nstart \\<= '1';\n\nwait for 50 us; -- Adjust delay to fit the new clock period\n\nstart \\<= '0';\n\nwait for 400 us; -- Adjust delay to fit the new clock period\n\nadjust\\_interval\\_up \\<= '1';\n\nwait for 20 us; -- Adjust delay to fit the new clock period\n\nadjust\\_interval\\_up \\<= '0';\n\nwait for 50 us; -- Adjust delay to fit the new clock period\n\nadjust\\_interval\\_down \\<= '1';\n\nwait for 20 us; -- Adjust delay to fit the new clock period\n\nadjust\\_interval\\_down \\<= '0';\n\nwait for 50 us; -- Adjust delay to fit the new clock period\n\n\\-- ...\n\n\\-- Stop the clock and hence terminate the simulation\n\nTbSimEnded \\<= '1';\n\nwait;\n\nend process;\n\nend tb;\n\n\\-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg\\_tb\\_Kitchen\\_Timer of tb\\_Kitchen\\_Timer is\n\nfor tb\n\nend for;\n\nend cfg\\_tb\\_Kitchen\\_Timer; \nAnd this is result of simulation:","removed":false,"published":"2023-08-30T12:25:19Z","deleted":false,"ap_id":"https://kbin.social/m/science/p/1508983/-/reply/2675833","local":false,"path":"0.1497215.1566279.1616298.1624063","distinguished":false,"language_id":0},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"counts":{"comment_id":1624063,"score":2,"upvotes":2,"downvotes":0,"published":"2023-08-30T12:25:19Z","child_count":16},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"subscribed":"NotSubscribed","saved":false,"creator_blocked":false},{"comment":{"id":1566279,"creator_id":1638447,"post_id":821313,"content":"[@T4V0](https://kbin.social/u/T4V0) Thanks for the answer, but I think I didn't understand you very well, can you send me the code with the modifications so that I know what exactly you mean? \nThank you very much, in advance","removed":false,"published":"2023-08-28T07:54:00Z","deleted":false,"ap_id":"https://kbin.social/m/science/p/1508983/-/reply/2617977","local":false,"path":"0.1497215.1566279","distinguished":false,"language_id":0},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"counts":{"comment_id":1566279,"score":1,"upvotes":1,"downvotes":0,"published":"2023-08-28T07:54:00Z","child_count":18},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"subscribed":"NotSubscribed","saved":false,"creator_blocked":false}],"posts":[{"post":{"id":821313,"name":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?","body":"Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?\n\n**Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.**\n\nThis is VHDL code:\n\n```\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nentity Kitchen_Timer is\n port (\n clk : in std_logic; -- Clock input\n reset : in std_logic; -- Reset input\n start : in std_logic; -- Start button input\n stop : in std_logic; -- Stop button input\n alarm : out std_logic -- Alarm output\n );\nend entity Kitchen_Timer;\n\n-- Declare the architecture for the kitchen timer\narchitecture Behavioral of Kitchen_Timer is\n signal count : integer range 0 to 3600 := 0; -- Counter for timer\n signal alarming : std_logic := '0'; -- Signal to indicate alarming interval\n signal alarm_en : std_logic := '0'; -- Signal to enable alarming interval\n signal alarm_cnt : integer range 0 to 600 := 0; -- Counter for alarming interval\nbegin\n -- Process to control the kitchen timer and alarming interval\n process (clk, reset)\n begin\n if (reset = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (rising_edge(clk)) then\n if (stop = '1') then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (start = '1' and count < 3600) then\n count <= count + 1;\n if (count = 3600) then\n count <= 0;\n alarming <= '0';\n alarm_en <= '0';\n alarm_cnt <= 0;\n elsif (count > 0) then\n alarm_en <= '1';\n end if;\n end if;\n\n if (alarm_en = '1') then\n if (alarm_cnt < 600) then\n alarm_cnt <= alarm_cnt + 1;\n else\n alarm_cnt <= 0;\n alarming <= '1';\n end if;\n end if;\n end if;\n end process;\n\n -- Assign the alarm output\n alarm <= alarming;\nend architecture Behavioral; ```\n\nThis is Testbench:\n\n```library ieee;\nuse ieee.std_logic_1164.all;\n\nentity tb_Kitchen_Timer is\nend tb_Kitchen_Timer;\n\narchitecture tb of tb_Kitchen_Timer is\n\n component Kitchen_Timer\n port (clk : in std_logic;\n reset : in std_logic;\n start : in std_logic;\n stop : in std_logic;\n alarm : out std_logic);\n end component;\n\n signal clk : std_logic;\n signal reset : std_logic;\n signal start : std_logic;\n signal stop : std_logic;\n signal alarm : std_logic;\n\n constant TbPeriod : time := 1000 ns; -- EDIT Put right period here\n signal TbClock : std_logic := '0';\n signal TbSimEnded : std_logic := '0';\n\nbegin\n\n dut : Kitchen_Timer\n port map (clk => clk,\n reset => reset,\n start => start,\n stop => stop,\n alarm => alarm);\n\n -- Clock generation\n TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';\n\n -- EDIT: Check that clk is really your main clock signal\n clk <= TbClock;\n\n stimuli : process\n begin\n -- EDIT Adapt initialization as needed\n start <= '0';\n stop <= '0';\n\n -- Reset generation\n -- EDIT: Check that reset is really your reset signal\n reset <= '1';\n wait for 100 ns;\n reset <= '0';\n wait for 100 ns;\n\n -- EDIT Add stimuli here\n wait for 100 * TbPeriod;\n\n -- Stop the clock and hence terminate the simulation\n TbSimEnded <= '1';\n wait;\n end process;\n\nend tb;\n\n-- Configuration block below is required by some simulators. Usually no need to edit.\n\nconfiguration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is\n for tb\n end for;\nend cfg_tb_Kitchen_Timer;```\n\n #science\n\n```","creator_id":1638447,"community_id":266,"removed":false,"locked":false,"published":"2023-08-23T14:29:04Z","updated":"2023-08-23T14:35:16Z","deleted":false,"nsfw":false,"ap_id":"https://kbin.social/m/science/p/1508983","local":false,"language_id":0,"featured_community":false,"featured_local":false},"creator":{"id":1638447,"name":"dejo","display_name":"dejo","banned":false,"published":"2023-08-23T14:23:13Z","actor_id":"https://kbin.social/u/dejo","local":false,"deleted":false,"bot_account":false,"instance_id":3},"community":{"id":266,"name":"science","title":"Science","description":"This magazine is dedicated to discussions on scientific discoveries, research, and theories across various fields, including physics, chemistry, biology, astronomy, and more. Whether you are a scientist, a science enthusiast, or simply curious about the world around us, this is the place for you. Here you can share your knowledge, ask questions, and engage in discussions on a wide range of scientific topics. From the latest breakthroughs to historical discoveries and ongoing research, this category covers a wide range of topics related to science.","removed":false,"published":"2023-04-17T17:34:25Z","updated":"2024-05-31T09:33:10Z","deleted":false,"nsfw":false,"actor_id":"https://kbin.social/m/science","local":false,"icon":"https://media.kbin.social/media/2e/f4/2ef4a5a77672d990bc755b6731902cf533a9e63a0fcb14d9897883176d0dc4a3.jpg","hidden":false,"posting_restricted_to_mods":false,"instance_id":3,"visibility":"Public"},"creator_banned_from_community":false,"banned_from_community":false,"creator_is_moderator":false,"creator_is_admin":false,"counts":{"post_id":821313,"comments":23,"score":1,"upvotes":1,"downvotes":0,"published":"2023-08-23T14:29:04Z","newest_comment_time":"2023-09-12T08:59:24Z"},"subscribed":"NotSubscribed","saved":false,"read":false,"hidden":false,"creator_blocked":false,"unread_comments":23}],"moderates":[]}