Expanded Steam gaming compatibility likely coming to Arm chips with hundreds of Windows games — Valve testing ARM64 Proton compatibility layer
Expanded Steam gaming compatibility likely coming to Arm chips with hundreds of Windows games — Valve testing ARM64 Proton compatibility layer
This could bode quite well for the future of Arm devices.
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From what I've understood of this - it's transpiling the x86 code to ARM on the fly. I honestly would have thought it wasn't possible but hearing that they're doing it - it will be a monumental effort, but very feasible. The best part is that once they've gotten CRT and cdecl instructions working - actual application support won't be far behind. The biggest challenge will likely be inserting memory barriers correctly - a spinlock implemented in x86 assembly is highly unlikely to work correctly without a lot of effort to recognize and transpile that specific structure as a whole.
There is an open source project that already does this a bit called box86 and box64.
I think you can find videos of people running Skyrim on arm chips like phones or maybe raspberry pi 5.
They don’t run well, but with more powerful chips and valves experience and money, I’m sure they can do it.
But does it run Doom? Using CMOV instructions only?
it's transpiling the x86 code to ARM on the fly. I honestly would have thought it wasn't possible
Apple’s been doing it for years. They try to do ahead of time transpiling wherever they can but they also do it on-the-fly for things like JITed code.
I thought FAT binaries don't work like that - they included multiple instruction sets with a header pointing to the sections (68k, PPC, and x86)
Rosetta to the best of my understanding did something similar - but relied on some custom microcode support that isn't rooted in ARM instructions. Do you have a link that explains a bit more in depth on how they did that?
Fat binaries contain both ARM and x86 code, but I was referring to Rosetta, which is used for x86-only binaries.
Rosetta does translation of x86 to ARM, both AOT and JIT. It does translate to normal ARM code, the only dependency on a Apple-specific custom ARM extension is that the M-series processors have a special mode that implements x86-like strong memory ordering. This means Rosetta does not have to figure out where to place memory barriers, this allows for much better performance.
So when running translated code Apple Silicon is basically an ARM CPU with an x86 memory model.
That makes a lot of sense - I wonder if they also do the SIGSEGV trick like HotSpot to know when they need to JIT the next chunk of instructions
